digital VLSI design

Comparators are a crucial part of modern digital VLSI design, serving as a fundamental building block. Although their logic design is straightforward, their widespread use in high-performance systems highlights the importance of optimizing their performance and power consumption. Hence, there is a constant need to improve the efficiency and effectiveness of comparator designs. A faster and power-efficient comparator is highly desirable. Therefore, we have designed three different comparators with static and dynamic styles using CMOS technology and CNTFET technology. The comparator we have designed is a 2-bit magnitude comparator, which uses the PTL design approach. We have created a Verilog-based netlist file to design the schematic, which is then simulated in the H-Spice tool to analyze the performance of the comparators.

Author(s) Details:

Ch. Ganesh,
Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India.

T. Sravan Kumar,
Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India.

S. Pallavi,
Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India.

G. Sai Preetham Reddy,
Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India.

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